Sudhanshu Nahata

As a research engineer at ASML, my primarily focus is creating technologies aimed at increasing throughput while lowering costs and energy usage for litho tools (also known as front-end semiconductor technology). This directly impacts the microchip production costs and enhances transistor density per unit area. My work often entails requirements management, stakeholder management, mechanical design (leveraging FEA), material selection and prototyping.

Prior to my current position, I had the privilege of working on back-end semiconductor technologies, particularly in the design and qualification of ultrasonic transducers for semiconductor ball-bonding and industrial wedge-bonding applications. This experience enriched my skillset in FEA-based design, PZT-material characterization, bode analysis, prototype development and testing. In addition, I had adeptly navigated internal and external customer esclations, devising actionable solutions that were seamlessly integrated into high-volume production lines.

Previously, I earned a Ph.D. in Mechanical Engineering from Carnegie Mellon University (CMU), with an emphasis on increasing the precision and reproducibility of a high-speed micro-scale manufacturing process (thesis link). My research revolved around the meticulous study of ultra-high-speed (UHS) spindles (used for processes such as micro-milling and micro-drilling) under both quasi-static and dynamic conditions. A brief summary of my work has been published as an article in the CMM magazine.